Timing models and delay calculations for integrated circuit cells are required for the design and implementation of an application specific integrated circuit ("ASIC") or an application specific standard product ("ASSP") integrated circuit ("IC"). Accurately characterized timing models are required to ensure that the ASIC or the ASSP implemented in silicon matches functional and timing specifications. Previous timing models were implemented as simple slope-intercept models that are a function of the output capacitance load. This function is based on simple first-order analysis of CMOS gate behavior. An example of such a model is: EQU TD=A+B*CL,
where TD is the time delay of a signal to propagate from the cell input to the cell output, A and B are delay coefficients extracted from transistor-level simulations and CL is the load capacitance.
These models were simple to implement and characterize for the design and verification process of ASICs or ASSPs. However, the accuracy of these linear models has become limited due to reductions in the process feature size (e.g., sub-micron) and the resulting prominence of second-order effects. The sub-micron CMOS gate delay is a nonlinear function of the input rise/fall time (also known as input slew rate) and the output load capacitance.
There are two approaches used to model and characterize this delay behavior: equations and tables. The equation model can be linear, exponential or a polynomial with a number of coefficients. The equation model can be based on curve fitting the simulated behavior of the cell or can be based on the inherent behavior of the CMOS cell. The inherent behavior corresponds to the physical properties of the cell. The analysis of circuit switching, however, is complex and is difficult to develop a closed form solution, except for a few special cases or when approximations are used in the analysis. In either case, the equation model can require a large number of coefficients and is difficult to characterize. Also, the approximations used to model the inherent behavior of the CMOS cell can limit the model accuracy or may not be valid for all of the integrated circuit cell types.
The other approach to characterizing and modeling the delay behavior is to use a table model which is a matrix of predetermined cell delay values based on various input rise/fall times and output load values. The cell delay value for specific input rise/fall times and output load values is then calculated by interpolating between the predetermined cell delay values. This essentially is a nonlinear curve fit to the cell behavior and can be accurate provided that there are sufficient predetermined cell delay values. Yet providing sufficient values requires a large number of predetermined cell delay values that impact characterization and implementation of the model in the design process. Despite this disadvantage, the nonlinear table model is the typical approach used by electronic design automation ("EDA") tools for the design of sub-micron integrated circuits, primarily because this is a more general and portable approach. Nonetheless, the efficient use of this nonlinear model does require limiting the total number of values in the models. As a result, accuracy is adversely affected.
Delay models can have qualified inaccuracies. Current linear logic-cell models, such as Symbios' VITA delay model for standard cells and gate-arrays, become inaccurate when a cell's input rise/fall time exceeds 2-3 ns. This is true for most cells, particularly under certain cell-specific load conditions.
This inaccuracy arises largely from the fact that these models are linear, whereas the dependence of cell delay on input rise/fall time is highly nonlinear. The VITA model, for example, uses the following equation for propagation delay (TD) calculations: EQU TD=A+B*CL+MC*MAX((TRF-0.1),0) (1)
where A, B, MC are VITA parameters, CL is the load capacitance, and TRF.sup.1 represents the cell input rise/fall time. This equation is based on the following assumptions:
1) Propagation delay at a given load CL varies linearly with TRF; PA1 2) Propagation delay varies linearly with CL for a given TRF; and PA1 3) The contributions to the propagation delay due to TRF and CL are independent of each other, and can be included to obtain the total correction. FNT .sup.1 For convenience, TRF is defined here as the peak-to-peak transition time. Alternate representations, such as 10%-90%, can be used without loss of generality. PA1 a) a first simulation point corresponding to low values of TRF and CL; PA1 b) a plurality of simulation points, each corresponding to a low TRF value and a moderate to high value of CL; and PA1 c) a plurality of different simulation points, each corresponding to a high TRF value and a low value of CL.
These assumptions are valid in general only for small rise/fall times, typically less than 1-2 ns. Consider a simple cell such as an inverter. The input rise/fall time TRF determines how long it takes for the inverter to cross the threshold voltage, as well as the variation of transistor resistances during capacitive charging and discharging. The effective resistance is therefore a function of TRF, as is the effective time constant--the transistor on-resistance multiplied by the load capacitance. As a consequence, the above assumptions are not valid for rise/fall times exceeding a few ns.
FIGS. 1 and 2 illustrate cell propagation delay vs. TRF for different load values for high-to-low (HL) and low-to-high (LH) transitions, respectively. FIGS. 3 and 4 show, respectively, delay vs. CL for a Symbios VGX500/INV inverter for different TRF values for HL and LH transitions. It can be clearly seen that the actual delay vs. input TRF characteristics are nonlinear functions of TRF as well as CL. The nonlinearity is more significant when input low to high transitions are involved. For particular simulated cells, at the rated low load capacitance value and TRF=10 ns, the error corresponding to the linear model for input HL transitions ranged from 5 to 130%, and for input LH transitions, from 40-450%. These results are in no way unusual compared to characteristics for other cells in this and other libraries. Note also that these models are typically derived from transistor-level simulations, such as provided by SPICE. Although highly accurate, the delay calculated by transistor-level simulations require an excessive amount of computational time.
The need remains, therefore, for a method of accurately modeling cell delay, preferably over a wide range of rise and fall times, and also for a range of load conditions in both standard and gate-array libraries. The method should also use a minimum number of transistor-level simulation inputs to reduce the time required for that simulation. The present inventions meets this need.